Datasheet

DATA1, DATA2,
DATA3, DATA4
t
(BCH)
1.4 V
1.4 V
1.4 V
BCK
LRCK
t
(BCL)
t
(LS)
t
(BCY)
t
(LH)
t
(DS)
t
(DH)
T0010-04
OVERSAMPLING RATE CONTROL
ZERO FLAG
PCM1680
SLES133B – MARCH 2005 – REVISED OCTOBER 2008 .................................................................................................................................................. www.ti.com
PARAMETER MIN UNIT
t
(BCY)
BCK pulse cycle time 1/(32 f
S
), 1/(48 f
S
), 1/(64 f
S
)
(1)
t
(BCH)
BCK pulse duration, HIGH 35 ns
t
(BCL)
BCK pulse duration, LOW 35 ns
t
(LS)
LRCK setup time to BCK rising edge 10 ns
t
(LH)
LRCK hold time to BCK rising edge 10 ns
t
(DS)
DATA1, DATA2, DATA3, DATA4 setup time 10 ns
t
(DH)
DATA1, DATA2, DATA3, DATA4 hold time 10 ns
(1) f
S
is the sampling frequency.
Figure 23. Audio Interface Timing
The PCM1680 automatically controls the oversampling rate of the delta-sigma DACs using the system clock
frequency. The oversampling rate is set to 64x oversampling with an 1152-f
S
, 768-f
S
, or 512-f
S
system clock; 32x
oversampling with a 384-f
S
or 256-f
S
system clock; and 16x oversampling with a 192-f
S
or 128-f
S
system clock.
The PCM1680 has two zero-flag pins, ZERO1 (pin 1) and ZERO2 (pin 28), which are assigned to the
combinations A through D as shown in Table 3 . Zero-flag combinations are selected using the zero-flag
combination bits, AZRO[1:0], located in control register 13 of the PCM1680. If the input data of the L-channel
and/or R-channel of all assigned channels remain at a logic-0 level for 1024 sampling periods (LRCK clock
periods), ZERO1 and ZERO2 are set to a logic-1 state, or high level. If the input data of any of the assigned
channels contain a logic-1, ZERO1, and ZERO2 are set to a logic-0 state immediately.
The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 10 to 1. The
reset default is active-high output or ZREV = 0.
Table 3. Zero-Flag Output Combinations
ZERO-FLAG COMBINATION ZERO1 (PIN 1) ZERO2 (PIN 28)
A DATA1 L-ch DATA1 R-ch
B N/A DATA[1:4]
C DATA4 DATA[1:3]
D DATA1 DATA[2:4]
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