Datasheet

POWER-ON-RESET FUNCTION
Reset Reset Release
V
CC
3.7 V
3 V
2.2 V
Internal Reset
System Clock
T0014-06
0 V
Don’t Care 3072 System Clocks
AUDIO SERIAL INTERFACE
PCM1680
www.ti.com .................................................................................................................................................. SLES133B – MARCH 2005 – REVISED OCTOBER 2008
The PCM1680 includes a power-on-reset function. Figure 21 shows the operation of this function. With the
system clock active and V
CC
> 3 V (typical, 2.2 V to 3.7 V), the power-on-reset function is enabled. The
initialization sequence requires 3072 system clocks from the time V
CC
> 3 V (typical, 2.2 V to 3.7 V). After the
initialization period, the PCM1680 is set to its reset default state, as described in the Mode Control Registers
section of this data sheet.
During the reset period (3072 system clocks), the analog output is forced to the common voltage (V
COM
), or
V
CC
/2. After the reset period, the internal registers are initialized in the next 1/f
S
period and if SCK, BCK, and
LRCK are provided continuously, the PCM1680 provides the proper analog output with group delay
corresponding to the input data.
Figure 21. Power-On-Reset Timing
The audio serial interface for the PCM1680 consists of a 6-wire synchronous serial port. It includes LRCK (pin 8),
BCK (pin 7), and DATA1 (pin 6), DATA2 (pin 11), DATA3 (pin 12), and DATA4 (pin 13). BCK is the serial audio
bit clock, and it is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the audio
interface serial shift register. Serial data are clocked into the PCM1680 on the rising edge of BCK. LRCK is the
serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous with the system clock. Ideally, it is recommended that LRCK and
BCK are derived from the system clock input, SCK. LRCK is operated at the sampling frequency, f
S
. BCK can be
operated at 32, 48, or 64 times the sampling frequency.
Internal operation of the PCM1680 is synchronized with LRCK. Accordingly, internal operation is suspended
when the sampling rate clock, LRCK, is changed or when SCK and/or BCK is interrupted at least for a 3-bit clock
cycle. If SCK, BCK, and LRCK are provided continuously after this suspended condition, the internal operation is
resynchronized automatically within the following 3/f
S
period. External resetting is not required.
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