Datasheet

SYSTEM CLOCK INPUT
t
w(SCKH)
System Clock
t
w(SCKL)
2 V
0.8 V
H
L
System Clock
Pulse Cycle
Time
(1)
T0005A08
PCM1680
SLES133B – MARCH 2005 – REVISED OCTOBER 2008 .................................................................................................................................................. www.ti.com
The PCM1680 requires a system clock for operating the digital interpolation filters and multilevel Δ Σ modulators.
The system clock is applied at the SCK (pin 5) input. Table 1 shows examples of system clock frequencies for
common audio sampling rates.
Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments ’ PLL170x multi-clock generator is an
excellent choice for providing the PCM1680 system clock source.
Table 1. System Clock Frequencies for Common Audio Sampling Frequencies
SAMPLING SYSTEM CLOCK FREQUENCY (f
SCK
), MHz
FREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
1152 f
S
8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216
16 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432
32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864
44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 —
(1)
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 —
(1)
88.2 kHz 11.2896 16.9344 22.5792 33.8688 —
(1)
—
(1)
—
(1)
96 kHz 12.288 18.432 24.576 36.864 —
(1)
—
(1)
—
(1)
192 kHz 24.576 36.864 —
(1)
—
(1)
—
(1)
—
(1)
—
(1)
(1) This system clock frequency is not supported for the given sampling frequency.
(1) 1/128 f
S
, 1/192 f
S
, 1/256 f
S
, 1/384 f
S
, 1/512 f
S
, 1/768 f
S
, or 1/1152 f
S
.
PARAMETER MIN MAX UNIT
t
w(SCKH)
System clock pulse duration, HIGH 7 ns
t
w(SCKL)
System clock pulse duration, LOW 7 ns
Figure 20. System Clock Timing
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