Datasheet


SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
9
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timing requirements (continued)
t
(BCKH)
Bit Clock Pulse
Cycle Time
†
BCK
t
(BCKL)
2.0 V
0.8 V
PARAMETERS
MIN MAX UNIT
t
(BCKH)
Bit clock pulse duration HIGH 10 ns
t
(BCKL)
Bit clock pulse duration LOW 10 ns
†
1/128 f
S
, 1/256 f
S
, and 1/512 f
S
.
Figure 4. Bit Clock Timing for TDM Format
DATA1
t
(BCH)
1.4
V
1.4
V
1.4
V
BCK
LRCK
t
(BCL)
t
(LB)
t
(BCY)
t
su(D)
t
h(D)
t
(BL)
PARAMETER
MIN MAX UNIT
t
(BCY)
BCK pulse cycle time 20 ns
t
(BCH)
BCK high-level time 10 ns
t
(BCL)
BCK low-level time 10 ns
t
(BL)
BCK rising edge to LRCK edge 7 ns
t
(LB)
LRCK falling edge to BCK rising edge 7 ns
t
su(D)
DATA setup time 7 ns
t
h(D)
DATA hold time 7 ns
Figure 5. Audio Interface Timing for TDM Format