Datasheet

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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
7
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timing requirements (continued)
audio serial interface
The audio serial interface for the PCM1606 comprises a 5-wire synchronous serial port. It includes LRCK (pin
18), BCK (pin 19), DATA1 (pin 1), DATA2 (pin 2) and DATA3 (pin 3). BCK is the serial audio bit clock and is used
to clock the serial data present on DATA1, DATA2, and DATA3 into the audio interface serial shift registers. Serial
data is clocked into the PCM1606 on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK
is used to latch serial data into the serial audio interface internal registers.
Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input or output, SCKI. The left/right clock, LRCK, is operated at the sampling
frequency (f
S
). The bit clock, BCK, may be operated at 32, 48, or 64 times the sampling frequency.
audio data formats and timing
The PCM1606 supports industry-standard audio data formats, including standard, I
2
S, left-justified, and TDM.
The data formats are shown in Figure 6. Data formats are selected using the format pins, FMT1 (pin 4) and
FMT0 (pin 5). All formats require binary 2s complement, MSB-first audio data. Figure 3 shows a detailed timing
diagram for the serial audio interface, with the exception of TDM format.
DATA1, DATA2, and DATA3 each carry two audio channels, designated as the left and right channels. The left
channel data always precedes the right channel data in the serial data stream for all data formats. Table 2 shows
the mapping of the digital input data to the analog output pins.
TDM format is able to interface by 3-wire synchronous serial port. All data inputs from DATA1, BCK can be
operated at 128, 256, and 512 times the sampling frequency. The rising edge of LRCK means the start of a data
frame. Only channel 1 and channel 2 data are acceptable at the 192-kHz sampling frequency (f
S
); channel 3,
channel 4, channel 5, and channel 6 data are don’t care.
Figure 4 shows the timing requirements for BCK input for TDM format. Figure 5 shows the detailed timing
diagram for TDM format.
Table 2. Audio Input Data to Analog Output Mapping
DATA INPUT CHANNEL ANALOG OUTPUT
DATA1 Left V
OUT
1
†
DATA1 Right V
OUT
2
†
DATA2 Left V
OUT
3
‡
DATA2 Right V
OUT
4
‡
DATA3 Left V
OUT
5
‡
DATA3 Right V
OUT
6
‡
†
Up to 192 kHz
‡
Up to 96 kHz