Datasheet

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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
6
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timing requirements (continued)
power-on reset functions
The PCM1606 includes a power-on reset function. Figure 2 shows the operation of this function. With the
system clock active and V
CC
> 3 V typical (2.2 V to 3.7 V), the power-on reset function is enabled. The
initialization sequence requires 1024 system clocks from the time V
CC
> 3 V. After the initialization period, the
PCM1606 is set to its reset default state.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
SAMPLING FREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
8 kHz — — 2.048 3.072 4.096 6.144
16 kHz — — 4.096 6.144 8.192 12.288
32 kHz — — 8.192 12.288 16.384 24.576
44.1 kHz — — 11.2896 16.9344 22.5792 33.8688
48 kHz — — 12.288 18.432 24.576 36.864
96 kHz — — 24.576 36.864 49.152 See Note 5
192 kHz 24.576 36.864 See Note 6 See Note 6 See Note 6 See Note 6
NOTES: 5. The 768-f
S
system clock rate is not supported for f
S
> 64 kHz.
6. This system clock is not supported for the given sampling frequency.
t
(SCKH)
System Clock
Pulse Cycle Time
†
System Clock
t
(SCKL)
2.0 V
0.8 V
†
1/128 f
S
, 1/256 f
S
, 1/384 f
S
, 1/512 f
S
and 1/768 f
S
.
PARAMETERS
MIN MAX UNIT
t
(SCKH)
System clock pulse duration HIGH 10 ns
t
(SCKL)
System clock pulse duration LOW 10 ns
Figure 1. System Clock Timing
1024 System Clocks
System Clock
Internal Reset
3.7 V
3.0 V
2.2 V
V
DD
0 V
Don’t Care
Reset Reset Removal
Figure 2. Power-On Reset Timing