Datasheet


SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
5
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electrical characteristics, all specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 44.1 kHz,
system clock = 384 f
S
and 24-bit data (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
PCM1606E
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
Passband
±0.03 dB 0.454 f
S
Passband
−3 dB
0.487 f
S
Stopband 0.546 f
S
Passband ripple ±0.03 dB
Stopband attenuation
Stopband = 0.546 f
S
−50
dB
Stopband attenuation
Stopband = 0.567 f
S
−55
dB
ANALOG FILTER PERFORMANCE
Frequency response At 20 kHz −0.03 dB
POWER SUPPLY REQUIREMENTS (see Note 4)
V
CC
Voltage range 4.5 5 5.5 VDC
f
S
= 44.1 kHz/384 f
S
50 65
I
CC
Supply current
f
S
= 96 kHz/256 f
S
72
mA
I
CC
Supply current
f
S
= 192 kHz/128 f
S
68
mA
f
S
= 44.1 kHz/384 f
S
250 358
Power dissipation
f
S
= 96 kHz/256 f
S
360
mW
Power dissipation
f
S
= 192 kHz/128 f
S
340
mW
TEMPERATURE RANGE
Operation temperature −25 85 °C
θ
JA
Thermal resistance 20-pin SSOP 115 °C/W
NOTES: 3. Analog performance specs are tested using System Two Cascade Plus by Audio Precision with 400-Hz HPF, 30-kHz LPF on at RMS
with 20-kHz LPF, 400-Hz HPF in calculation.
Shibasoku #725 THD meter, 400 Hz HPF, 30 kHz LPF on, at average mode with 20-kHz bandwidth limiting. The load connected
to the analog output is 5 kΩ or larger via capacitance coupling.
4. Condition in 192-kHz operation is channel 3 through channel 6 are disabled.
timing requirements
system clock input
The PCM1606 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI (pin 20). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an
excellent choice for providing the PCM1606 system clock source.
The 192-kHz sampling frequency operation is available on DATA1 for V
OUT
1 and V
OUT
2. When the system clock
of 128 f
S
or 192 f
S
is detected, V
OUT
3, V
OUT
4, V
OUT
5 and V
OUT
6 are automatically forced to the bipolar zero
level (= 0.5 V
CC
). Table 1 lists the typical system clock frequency.