Datasheet

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SLES014B − OCTOBER 2001 − REVISED AUGUST 2002
19
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APPLICATION INFORMATION
connection diagrams
A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decoupling
components. Texas Instruments recommends using the component values shown in Figure 28 for all designs.
A typical application diagram is shown in Figure 29. Texas Instruments’ PLL1700 is used to generate the system
clock input at SCKI, as well as generating the clock for the audio signal processor.
The use of series resistors (22 Ω to 100 Ω) is recommended for SCKI, LRCK, BCK, DATA1, DATA2, and DATA3.
The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which
removes high-frequency noise from the digital signal, thus, reducing high-frequency emission.
DATA1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
+
PCM1606
DATA2
DATA3
FMT1
FMT0
ZEROA
AGND
V
OUT
5
V
OUT
6
V
OUT
1
SCKI
V
OUT
4
BCK
LRCK
DEMP1
DEMP0
V
OUT
3
V
OUT
2
V
COM
V
CC
10 µF
Microcontroller
ML
PLL1700
MC
MD
10 µF
+
+5 V Power Supply
BCK
LRCK
DEMP1
DEMP0
LPF
LPF
LPF
DATA1
DATA2
DATA3
FMT1
FMT0
ZEROA
LPF
LPF
LPF
SCKO3
Figure 28. Basic Connection Diagram