Datasheet

6–5
6.6 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (see Note 5 and Figure 6–1 and Figure 6–4)
ALTERNATE
SYMBOL
TEST CONDITIONS MIN MAX UNIT
t
Propagation delay time
PCLK to shared signal
valid delay time
t
val
C 50 pF See Note 6
11
ns
t
pd
Propagation delay time
PCLK to shared signal
invalid delay time
t
inv
C
L
= 50 pF, See Note 6
2
ns
t
en
Enable time,
high-impedance-to-active delay time from PCLK
t
on
2 ns
t
dis
Disable time,
active-to-high-impedance delay time from PCLK
t
off
28 ns
t
su
Setup time before PCLK valid t
su
, See Note 4 7 ns
t
h
Hold time after PCLK high t
h
, See Note 4 0 ns
5. This data sheet uses the following conventions to describe time (t) intervals. The format is: t
A
, where subscript A indicates the type
of dynamic parameter being represented. One of the following is used: t
pd
= propagation delay time, t
d
= delay time, t
su
= setup time,
and t
h
= hold time.
6. PCI shared signals are AD31–AD0, C/BE3
–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.