Datasheet

6–4
6.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature (see Figure 6–2 and Figure 6–3)
ALTERNATE
SYMBOL
MIN MAX UNIT
t
c
Cycle time, PCLK t
cyc
30 ∞ ns
t
wH
Pulse duration, PCLK high t
high
11 ns
t
wL
Pulse duration, PCLK low t
low
11 ns
∆v/∆t Slew rate, PCLK t
r
, t
f
1 4 V/ns
t
w
Pulse duration, RSTIN t
rst
1 ms
t
su
Setup time, PCLK active at end of RSTIN (see Note 4 ) t
rst-clk
100 ms
NOTE 4: The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI
close.