Datasheet

5–23

5.29 Hot Swap Control Status Register

The hot swap control status register contains control and status information for CPCI hot swap resources. See

Table 5–22 for a complete description of the register contents.

Bit 7 6 5 4 3 2 1 0

Name Hot swap control status

Type R/C/U R/C/U R R R/W R R/W R

Default 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: E6h

Default: 00h

Table 5–22. Hot Swap Control Status Register

BIT TYPE FUNCTION

7 R/C/U

ENUM insertion status. When set, the ENUM output is driven by the PCI2250. This bit defaults to 0, and will be set after

a PCI reset occurs, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set following an insertion when the board

implementing the PCI2250 is ready for configuration. This bit cannot be set under software control.

6 R/C/U

ENUM extraction status. When set, the ENUM output is driven by the PCI2250. This bit defaults to 0, and is set when the

ejector handle is opened and bit 7 is 0. Thus, this bit is set when the board implementing the PCI2250 is about to be removed.

This bit cannot be set under software control.

5–4 R Reserved. Bits 5 and 4 return 0s when read.

3 R/W

LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HSLED) under normal conditions. However,

for a duration following a PCI_RST

, the HSLED output is driven high by the PCI2250 and this bit is ignored. When this bit

is interpreted, a 1 will cause HSLED high and a 0 will cause HSLED low.

Following PCI_RST

, the HSLED output is driven high by the PCI2250 until the ejector handle is closed. When these

conditions are met, the HSLED is under software control via this bit.

2 R Reserved. Bit 2 returns 0 when read.

1 R/W

ENUM interrupt mask. This bit allows the HSENUM output to be masked by software. Bits 6 and 7 are set independently

from this bit.

0 = Enable HSENUM

output

1 = Mask HSENUM

output

0 R Reserved. Bit 0 returns 0 when read.