Datasheet

5–21

5.25 PMCSR Bridge Support Register

The PMCSR bridge support register is required for all PCI bridges and supports PCI bridge specific functionality. See

Table 5–21 for a complete description of the register contents.

Bit 7 6 5 4 3 2 1 0

Name PMCSR bridge support

Type R R R R R R R R

Default X X 0 0 0 0 0 0

Type: Read-only

Offset: E2h

Default: X0h

Table 5–21. PMCSR Bridge Support Register

BIT TYPE FUNCTION

7 R

Bus power control enable. This bit returns the value of the MS1/BCC input.

0 = Bus power/ clock control disabled

1 = Bus power/clock control enabled

6 R

B2/B3 support for D3

hot

. This bit returns the value of MS1/BCC input. When this bit is 1, the secondary clocks

are stopped when the device is placed in D3

hot

. When this bit is 0, the secondary clocks remain on in all device

states.

Note: If the primary clock is stopped, then the secondary clocks will stop because the primary clock is used to

generate the secondary clocks.

5–0 R Reserved. Bits 5–0 return 0s when read.

5.26 Data Register

The data register is an optional, 8-bit read–only register that provides a mechanism for the function to report

state-dependent operating data such as power consumed or heat dissipatin. The PCI2050 does not implement the

data register.

Bit 7 6 5 4 3 2 1 0

Name Data

Type R R R R R R R R

Default 0 0 0 0 0 0 0 0

Type: Read-only

Offset: E3h

Default: 00h