Datasheet

5–17
5.19 Secondary Clock Control Register
The secondary clock control register is used to control the secondary clock outputs. See Table 5–17 for a complete
description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Secondary clock control
Type R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Secondary clock control
Type: Read-only, Read/Write
Offset: 68h
Default: 0000h
Table 5–17. Secondary Clock Control Register
BIT TYPE FUNCTION
15–9 R Reserved. Bits 15–9 return 0s when read.
8 R/W
Clockout4 disable.
0 = Clockout4 enabled (default)
1 = Clockout4 disabled and driven high
7–6 R/W
Clockout3 disable.
00, 01, 10 = Clockout3 enabled (00 default)
11 = Clockout3 disabled and driven high
5–4 R/W
Clockout2 disable.
00, 01, 10 = Clockout2 enabled (00 default)
11 = Clockout2 disabled and driven high
3–2 R/W
Clockout1 disable.
00, 01, 10 = Clockout1 enabled (00 default)
11 = Clockout1 disabled and driven high
1–0 R/W
Clockout0 disable.
00, 01, 10 = Clockout0 enabled (00 default)
11 = Clockout0 disabled and driven high