Datasheet

5–15
5.17 Arbiter Timeout Status Register
The arbiter timeout status register contains the status of each request (request 5–0) timeout. The timeout status bit
for the respective request is set if the device did not assert FRAME after 16 clocks. See Table 5–15 for a complete
description of the register contents.
Bit 7 6 5 4 3 2 1 0
Name Arbiter timeout status
Type R R R R R/C/U R/C/U R/C/U R/C/U
Default 0 0 0 0 0 0 0 0
Register: Arbiter timeout status
Type: Read-only
Offset: 63h
Default: 00h
Table 5–15. Arbiter Timeout Status Register
BIT TYPE FUNCTION
7–4 R Reserved. Bits 7–4 return 0s when read.
3 R/C/U
Request 3 timeout status. Cleared by writing a 1.
0 = No timeout (default)
1 = Timeout has occurred
2 R/C/U
Request 2 timeout status. Cleared by writing a 1.
0 = No timeout (default)
1 = Timeout has occurred
1 R/C/U
Request 1 timeout status. Cleared by writing a 1.
0 = No timeout (default)
1 = Timeout has occurred
0 R/C/U
Request 0 timeout status. Cleared by writing a 1.
0 = No timeout (default)
1 = Timeout has occurred