Datasheet

5–14

5.16 Arbiter Request Mask Register

The arbiter request mask register contains the SERR enable on arbiter timeouts and the request mask controls. See

Table 5–14 for a complete description of the register contents.

Bit 7 6 5 4 3 2 1 0

Name Arbiter request mask

Type R R/W R R R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: 62h

Default: 00h

Table 5–14. Arbiter Request Mask Register

BIT TYPE FUNCTION

7 R Reserved. Bit 7 returns 0 when read.

6 R/W

Timeout automatic masking enable

0 = Masking not automatic (default)

1 = Allow masking after 16-clock timeout

5–4 R Reserved. Bits 5 and 4 return 0s when read.

3 R/W

Request 3 (REQ3) mask bit

0 = Use request 3 (default)

1 = Ignore request 3

2 R/W

Request 2 (REQ2) mask bit

0 = Use request 2 (default)

1 = Ignore request 2

1 R/W

Request 1 (REQ1) mask bit

0 = Use request 1 (default)

1 = Ignore request 1

0 R/W

Request 0 (REQ0) mask bit

0 = Use request 0 (default)

1 = Ignore request 0