Datasheet

5–13
5.15 Diagnostic Status Register
The diagnostic status register is used to reflect the bridge diagnostic status. See Table 5–13 for a complete
description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Diagnostic status
Type R R R R
R/C/
U
R/C/
U
R R
R/C/
U
R R R R R R
R/C/
U
Default 0 0 0 0 X X 0 0 0 0 0 0 0 X X X
Register: Diagnostic status
Type: Read-only, Read/Write
Offset: 5Eh
Default: 0X0Xh
Table 5–13. Diagnostic Status Register
BIT TYPE FUNCTION
15–12 R Reserved. Bits 15–12 return 0s when read.
11 R/C/U
Bridge detected a parity error while mastering on the secondary bus. When set, bit 11 indicates that the secondary bus
master detected a parity error. Writing a 1 to this bit clears it.
0 = No parity error detected
1 = Parity error detected
10 R/C/U
Bridge detected a parity error while mastering on the primary bus. When set, bit 10 indicates that the primary bus master
detected a parity error. Writing a 1 to this bit clears it.
0 = No parity error detected
1 = Parity error detected
9 R MS1 status. Returns the logical value of the MS1/BPCC input.
8 R MS0 status. Returns the logical value of the MS0 input.
7 R/C/U
Arbiter timeout SERR status. When set, bit 0 indicates that SERR has occurred due to the expiration of the arbiter timer.
Writing a 1 to this bit clears it.
0 = No SERR (default)
1 = SERR occurred due to an arbiter timeout
6 R Reserved. Bit 6 returns 0 when read.
5 R HS_SWITCH status. This registers returns the logical value of the S_MFUNC input regardless of the value of MS0/MS1.
4–3 R Reserved
2 R
External arbiter enable pin status. Bit 2 contains the current state of the external pin external arbiter enable.
0 = Signal low
1 = Signal high
1 R
Serial EEPROM block status. Bit 1 indicates the status of the serial EEPROM block. When set, bit 1 indicates that the serial
EEPROM block is busy.
0 = Serial EEPROM block not busy
1 = Serial EEPROM block busy
0 R/C/U
Arbiter timeout status. Bit 0 indicates the status of the arbiter timer. When set, bit 0 indicates that a bus master did not begin
the cycle within 16 clocks. Writing a 1 to this bit clears it. This bit is encoded as:
0 = No timeout (default).
1 = Master requesting the bus did not start cycle within 16 clocks.