Datasheet

5–4

5.4 Extension Window Base 0, 1 Registers

The bridge supports two extension windows that define an address range decoded as described in the window enable

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Extension window base 0, 1

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Extension window base 0, 1

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: 44h, 4Ch

Default: 0000 0000h

5.5 Extension Window Limit 0, 1 Registers

The bridge supports two extension windows. Each window defines an address range that is decoded as described

in the window enable register and window map register. The extension window limit registers define the 32-bit limit

address of the window.

Bits 0 and 1 of this register determine whether the extension window is a prefetchable memory window, a

nonprefetchable window, or an I/O window. These bits are encoded as:

00 = Nonprefetchable memory

01 = Prefetchable memory

1x = I/O

Memory windows have a 4–Kbyte granularity and I/O windows have a doubleword (4-byte) granularity. When a

memory window is selected, bits 11–2 have no effect and are assumed to be 1s for the limit register and 0s for the

base register. This is consistent with the 4K-byte granularity of the memory windows.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Extension window limit 0, 1

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Extension window limit 0, 1

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write

Offset: 48h, 50h

Default: 0000 0000h