Datasheet

4–14
4.29 Expansion ROM Base Address Register
The PCI2250 does not implement the expansion ROM remapping feature. The expansion ROM base address
register returns all 0s when read.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Expansion ROM base address
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Expansion ROM base address
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Expansion ROM base address
Type: Read-only
Offset: 38h
Default: 0000 0000h
4.30 Interrupt Line Register
The interrupt line register is read/write and is used to communicate interrupt line routing information. Since the bridge
does not implement an interrupt signal terminal, this register defaults to FFh.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1
Register: Interrupt line
Type: Read/write
Offset: 3Ch
Default: FFh
4.31 Interrupt Pin Register
The bridge default state does not implement any interrupt terminals. Reads from bits 7–0 of this register return 0s.
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Interrupt pin
Type: Read-only
Offset: 3Dh
Default: 00h