Datasheet

4–13
4.26 I/O Base Upper 16 Bits Register
The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address
that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I/O base upper 16 bits
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: I/O base upper 16 bits
Type: Read/Write
Offset: 30h
Default: 0000h
4.27 I/O Limit Upper 16 Bits Register
The I/O limit upper 16-bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address
that specifies the upper limit of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I/O limit upper 16 bits
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: I/O limit upper 16 bits
Type: Read/Write
Offset: 32h
Default: 0000h
4.28 Capability Pointer Register
The capability pointer register provides the pointer to the PCI configuration header where the PCI power management
register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The
capability pointer register is read-only and returns DCh when read, indicating the power management registers are
located at PCI header offset DCh.
Bit 7 6 5 4 3 2 1 0
Name Capability pointer register
Type R R R R R R R R
Default 1 1 0 1 1 1 0 0
Register: capability pointer
Type: Read-only
Offset: 34h
Default: DCh