Datasheet

4–4
4.4 Status Register
The status register provides device information to the host system. This register is read-only. Bits in this register are
cleared by writing a 1 to the respective bit; writing a 0 to a bit location has no effect. Table 4–4 describes the status
register.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Status
Type
R/C/
U
R/C/
U
R/C/
U
R/C/
U
R/C/
U
R R
R/C/
U
R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Register: Status
Type: Read-only, Read/Clear/Update
Offset: 06h
Default: 0210h
Table 4–4. Status Register
BIT TYPE FUNCTION
15 R/C/U Detected parity error. Bit 15 is set when a parity error is detected.
14 R/C/U
Signaled system error (SERR). Bit 14 is set if SERR is enabled in the command register (offset 04h, see Section 4.3) and
the bridge signals a system error (SERR). See Section 3.9,
System Error Handling .
0 = No SERR signaled (default)
1 = Signals SERR
13 R/C/U
Received master abort. Bit 13 is set when a cycle initiated by the bridge on the primary bus has been terminated by a master
abort.
0 = No master abort received (default)
1 = Master abort received
12 R/C/U
Received target abort. Bit 12 is set when a cycle initiated by the bridge on the primary bus has been terminated by a target
abort.
0 = No target abort received (default)
1 = Target abort received
11 R/C/U
Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the primary bus with a target abort.
0 = No target abort signaled by the bridge (default)
1 = Target abort signaled by the bridge
10–9 R
DEVSEL timing. These read-only bits encode the timing of P_DEVSEL and are hardwired 01b, indicating that the bridge
asserts this signal at a medium speed.
01 = Hardwired (default)
8 R/C/U
Data parity error detected. Bit 8 is encoded as:
0 = The conditions for setting this bit have not been met. No parity error detected. (default)
1 = A data parity error occurred and the following conditions were met:
a. P_PERR
was asserted by any PCI device including the bridge.
b. The bridge was the bus master during the data parity error.
c. Bit 6 (parity error response enable) is set in the command register (offset 04h, see Section 4.3).
7 R
Fast back-to-back capable. The bridge does not support fast back-to-back transactions as a target; therefore, bit 7 is
hardwired to 0.
6 R
User-definable feature (UDF) support. The PCI2250 does not support the user-definable features; therefore, bit 6 is
hardwired to 0.
5 R 66-MHz capable. The PCI2250 operates at a maximum P_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0.
4 R
Capabilities list. Bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power management capabilities is implemented by this function.
3–0 R Reserved. Bits 3–0 return 0s when read.