Datasheet

4–1
4 Bridge Configuration Header
The PCI2250 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI
Bridge Architecture Specification . Table 4–1 shows the PCI configuration header, which includes the predefined
portion of the bridge’s configuration space. The PCI configuration offset is shown in the right column under the
OFFSET heading.
Table 4–1. Bridge Configuration Header
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Primary latency timer Cache line size 0Ch
Base address register 0 10h
Base address register 1 14h
Secondary bus latency timer Subordinate bus number Secondary bus number Primary bus number 18h
Secondary status I/O limit I/O base 1Ch
Memory limit Memory base 20h
Prefetchable memory limit Prefetchable memory base 24h
Prefetchable base upper 32 bits 28h
Prefetchable limit upper 32 bits 2Ch
I/O limit upper 16 bits I/O base upper 16 bits 30h
Reserved Capability pointer 34h
Expansion ROM base address 38h
Bridge control Interrupt pin Interrupt line 3Ch
Arbiter control Extended diagnostic Chip control 40h
Extension window base 0 44h
Extension window limit 0 48h
Extension window base 1 4Ch
Extension window limit 1 50h
Primary decode control Secondary decode control Extension window map Extension window enable 54h
Clock run control Port decode map Buffer control Port decode enable 58h
Diagnostic status Diagnostic control 5Ch
Arbiter timeout status Arbiter mask control Reserved 60h
Reserved P_SERR event disable 64h
Reserved P_SERR status Secondary clock control 68h
Reserved 6Ch–D8h
Power management capabilities PM next item pointer PM capability ID DCh
Data PMCSR bridge support Power management control/status E0h
Reserved Hot-swap control status HS next item pointer HS capability ID E4h
Reserved E8h–FFh