Datasheet

3–4
PCI Bus 0
Primary Bus 00h
Secondary Bus 01h
Subordinate Bus 02h
PCI2250
Primary Bus 00h
Secondary Bus 03h
Subordinate Bus 03h
PCI2250
PCI Bus 1 PCI Bus 3
Primary Bus 01h
Secondary Bus 02h
Subordinate Bus 02h
PCI2250
PCI Bus 2
Figure 3–4. Bus Hierarchy and Numbering
3.4 Special Cycle Generation
The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. During a type 1
configuration cycle, if the bus number field matches the bridge secondary bus number, then the device number field
is 1Fh, the function number field is 07h, and the bridge generates a special cycle on the secondary bus with a message
that matches the type 1 configuration cycle data. If the bus number is a subordinate bus and not the secondary bus,
then the bridge passes the type 1 special cycle request through to the secondary interface along with the proper
message.
Special cycles are never passed through the bridge. Type 1 configuration cycles with a special cycle request can
propagate in both directions.
3.5 Secondary Clocks
The PCI2250 provides five secondary clock outputs (S_CLKOUT[0:4]). Four are provided for clocking secondary
devices. The fifth clock should be routed back into the PCI2250 S_CLK input to ensure all secondary bus devices
see the same clock.