Datasheet

3–3
The bridge claims only type 0 configuration cycles when its P_IDSEL terminal is asserted during the address phase
of the cycle and the PCI function number encoded in the cycle is 0. If the function number is 1 or greater, the bridge
does not recognize the configuration command. In this case, the bridge does not assert DEVSEL and the
configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles
by accessing internal registers from the configuration header.
Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles
based on the bus number of the destination bus. Figure 3–3 shows the P_AD bus encoding during the address phase
of a type 1 cycle. The device number and bus number fields define the destination bus and device for the cycle.
Reserved
Register
Number
31
Function
Number
11 10 78
00
102
24
Bus Number
23 16
Device
Number
15
Figure 3–3. PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle
Several bridge configuration registers shown in Table 4–1 are significant when decoding and claiming type 1
configuration cycles. The destination bus number encoded on the P_AD bus is compared to the values programmed
in the bridge configuration registers 18h, 19h, and 1Ah, which are the primary bus number, secondary bus number,
and subordinate bus number registers, respectively. These registers default to 00h and are programmed by host
software to reflect the bus hierarchy in the system (see Figure 3–4 for an example of a system bus hierarchy and how
the PCI2250 bus number registers would be programmed in this case).
When the PCI2250 claims a type 1 configuration cycle that has a bus number equal to its secondary bus number,
the PCI2250 converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the proper S_AD line
as the IDSEL (see Table 3–2). All other type 1 transactions that access a bus number greater than the bridge
secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration
cycles.
Table 3–2. PCI S_AD31–S_AD16 During Address Phase of a Type 0 Configuration Cycle
DEVICE
NUMBER
SECONDARY IDSEL
S_AD31–S_AD16
S_AD
ASSERTED
0h 0000 0000 0000 0001 16
1h 0000 0000 0000 0010 17
2h 0000 0000 0000 0100 18
3h 0000 0000 0000 1000 19
4h 0000 0000 0001 0000 20
5h 0000 0000 0010 0000 21
6h 0000 0000 0100 0000 22
7h 0000 0000 1000 0000 23
8h 0000 0001 0000 0000 24
9h 0000 0010 0000 0000 25
Ah 0000 0100 0000 0000 26
Bh 0000 1000 0000 0000 27
Ch 0001 0000 0000 0000 28
Dh 0010 0000 0000 0000 29
Eh 0100 0000 0000 0000 30
Fh 1000 0000 0000 0000 31
10h–1Eh 0000 0000 0000 0000 –