Datasheet

2–11
Table 2–10. Secondary PCI Interface Control
TERMINAL
NAME
PCM
NUMBER
PGF
NUMBER
I/O DESCRIPTION
S_DEVSEL 7 9 I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target
device. As a PCI initiator on the secondary bus, the bridge monitors S_DEVSEL
until a target
responds. If no target responds before a timeout occurs, then the bridge terminates the cycle
with a master abort.
S_FRAME 11 13 I/O
Secondary cycle frame. S_FRAME is driven by the initiator of a secondary bus cycle.
S_FRAME
is asserted to indicate that a bus transaction is beginning and data transfers
continue while S_FRAME
is asserted. When S_FRAME is deasserted, the secondary bus
transaction is in the final data phase.
S_GNT3
S_GNT2
S_GNT1
S_GNT0
47
45
44
43
53
51
50
49
O
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals
are used to grant potential secondary PCI masters access to the bus. Five potential initiators
(including the bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0
is reconfigured as an external secondary bus
request signal for the bridge.
S_IRDY 10 12 I/O
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus initiator to
complete the current data phase of the transaction. A data phase is completed on a rising
edge of S_CLK where both S_IRDY
and S_TRDY are asserted. Until S_IRDY and S_TRDY
are both sample asserted, wait states are inserted.
S_PAR 2 3 I/O
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even
parity across the S_AD and S_C/BE
buses. As an initiator during PCI write cycles, the bridge
outputs this parity indicator with a one-S_CLK delay. As a target during PCI read cycles, the
calculated parity is compared to the initiator parity indicator. A miscompare can result in a
parity error assertion (S_PERR
).
S_PERR
4 6 I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to
indicate that calculated parity does not match S_PAR when S_PERR
is enabled through
bit 6 of the command register (offset 04h, see Section 4.3).
S_REQ3
S_REQ2
S_REQ1
S_REQ0
42
39
38
37
47
42
40
39
I
Secondary PCI bus request signals. The bridge provides internal arbitration, and these
signals are used as inputs from secondary PCI bus initiators requesting the bus. Five
potential initiators (including the bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, the S_REQ0
signal is reconfigures as an external
secondary bus grant for the bridge.
S_SERR
3 5 I
Secondary system error. S_SERR is passed through the primary interface by the bridge if
enabled through the bridge control register (offset 3Eh, see Section 4.32). S_SERR
is never
asserted by the bridge.
S_STOP 6 8 I/O
Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop
the current secondary bus transaction. S_STOP
is used for target disconnects and is
commonly asserted by target devices that do not support burst data transfers.
S_TRDY 9 11 I/O
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to
complete the current data phase of the transaction. A data phase is completed on a rising
edge of S_CLK where both S_IRDY
and S_TRDY are asserted. Until S_IRDY and S_TRDY
are both sample asserted, wait states are inserted.