Datasheet

1–1
1 Introduction
1.1 Description
The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high-performance connection path between two
peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets
on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge
supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act
independently.
The PCI2050 bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical
loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The
PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with
an external secondary PCI bus arbiter.
The CompactPCI hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for
multifunction CompactPCI cards and for adapting single-function cards to hot-swap compliance.
The PCI2050 bridge is compliant with the PCI-to-PCI Bridge Specification 1.1. The PCI2050 provides compliance
for PCI Power Management 1.0 and 1.1. The PCI2050 has been designed to lead the industry in power conservation.
An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates
up to 33 MHz.
The PCI2050I is an industrial version of the PCI2050 that has a larger operating temperature range. All references
to the PCI2050 also apply to the PCI2050I unless otherwise noted.
1.2 Features
The PCI2050 supports the following features:
• Architecture configurable for PCI Bus Power Management Interface Specification
• CompactPCI hot-swap-friendly silicon
• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Two 32-bit, 33-MHz PCI buses
• Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus
arbiter
• Burst data transfers with pipeline architecture to maximize data throughput in both directions
• Independent read and write buffers for each direction
• Up to three delayed transactions in both directions
• Ten secondary PCI clock outputs
• Predictable latency per PCI Local Bus Specification
• Bus locking propagation
• Secondary bus is driven low during reset
• VGA/palette memory and I/O decoding options
• Advanced submicron, low-power CMOS technology
• 208-terminal QFP or 209-terminal MicroStar BGA package