Datasheet

vii
List of Tables
Table Title Page
2–1 208-Terminal PDV Signal Names Sorted by Terminal Number 2–3. . . . . . . .
2–2 209-Terminal GHK/ZHK Signal Names Sorted by Terminal Number 2–5. . .
2–3 Signal Names Sorted Alphabetically 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Primary PCI System Terminals 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Primary PCI Address and Data Terminals 2–9. . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Primary PCI Interface Control Terminals 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Secondary PCI System Terminals 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Secondary PCI Address and Data Terminals 2–12. . . . . . . . . . . . . . . . . . . . . . .
2–9 Secondary PCI Interface Control Terminals 2–13. . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Miscellaneous Terminals 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 JTAG Interface Terminals 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 Power Supply Terminals 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PCI Command Definition 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI S_AD31–S_AD16 During the Address Phase of a Type 0
Configuration Cycle 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Configuration via MS0 and MS1 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 JTAG Instructions and Op Codes 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Boundary Scan Terminal Order 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Clock Mask Data Format 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Bridge Configuration Header 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Command Register Description 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Status Register Description 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Secondary Status Register Description 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Bridge Control Register Description 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Chip Control Register Description 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Extended Diagnostic Register Description 5–2. . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Arbiter Control Register Description 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 P_SERR Event Disable Register Description 5–4. . . . . . . . . . . . . . . . . . . . . . .
5–5 GPIO Output Data Register Description 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 GPIO Output Enable Register Description 5–5. . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 GPIO Input Data Register Description 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Secondary Clock Control Register Description 5–7. . . . . . . . . . . . . . . . . . . . . .
5–9 P_SERR Status Register Description 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Power-Management Capabilities Register Description 5–9. . . . . . . . . . . . . . .
5–11 Power-Management Control/Status Register Description 5–10. . . . . . . . . . . . .
5–12 PMCSR Bridge Support Register Description 5–11. . . . . . . . . . . . . . . . . . . . . . .
5–13 Hot-Swap Control Status Register Description 5–13. . . . . . . . . . . . . . . . . . . . . .