Datasheet
6–2
6.3 Recommended Operating Conditions for PCI Interface
OPERATION MIN NOM MAX UNIT
V
CC
Core voltage Commercial 3.3 V 3 3.3 3.6 V
PV
PCI supply voltage
Commercial
3.3 V 3 3.3 3.6
V
P_V
CCP
PCI supply voltage Commercial
5 V 4.75 5 5.25
V
SV
PCI supply voltage
Commercial
3.3 V 3 3.3 3.6
V
S_V
CCP
PCI supply voltage Commercial
5 V 4.75 5 5.25
V
V
Input voltage
3.3 V 0 V
CCP
V
V
I
Input voltage
5 V
0 V
CCP
V
V
†
Output voltage
3.3 V 0 V
CCP
V
V
O
†
Output voltage
5 V
0 V
CCP
V
V
‡
High le el inp t oltage
CMOS compatible
3.3 V 0.5 V
CCP
V
V
IH
‡
High-level input voltage
CMOS compatible
5 V 2
V
V
‡
Low level input voltage
CMOS compatible
3.3 V 0.3 V
CCP
V
V
IL
‡
Low-level input voltage
CMOS compatible
5 V
0.8
V
†
Applies to external output buffers
‡
Applies to external input and bidirectional buffers without hysteresis
6.4 Electrical Characteristics Over Recommended Operating Conditions
PARAMETER TERMINALS OPERATION TEST CONDITIONS MIN MAX UNIT
3.3 V
I
OH
= –0.5 mA
0.9 V
CC
V
V
OH
High-level output voltage
5 V
I
OH
= –2 mA
2.4
V
OH
g e e ou u o age
TTL 5 V I
OH
= –1.4 mA 2.4
V
Low level output voltage
3.3 V
I
OL
= 1.5 mA
0.1 V
CC
V
V
OL
Low-level output voltage
5 V
I
OL
= 6 mA
0.55
V
I
High level input current
Input terminals, PCI V
I
= V
CCP
10
A
I
IH
High-level input current
I/O terminals
†
VV
10
µA
IH
g
I/O terminals
†
V
I
= V
CCP
10
µ
I
Low level input current
Input terminals, PCI
V GND
–1
A
I
IL
Low-level input current
I/O terminals
†
V
I
= GND
–10
µA
I
OZ
High-impedance output current V
O
= V
CCP
or GND ±10 µA
†
For I/O terminals, the input leakage current includes the off-state output current I
OZ
.
‡
For TTL signals, I
OH
= 1.4 mA is the test condition for the industrial-temperature-range PCI2050I.
6.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature (see Figure 6–2 and Figure 6–3)
ALTERNATE
SYMBOL
MIN MAX UNIT
t
c
Cycle time, PCLK t
cyc
30 ∞ ns
t
wH
Pulse duration, PCLK high t
high
11 ns
t
wL
Pulse duration, PCLK low t
low
11 ns
∆v/∆t Slew rate, PCLK t
r
, t
f
1 4 V/ns
t
w
Pulse duration, RSTIN t
rst
1 ms
t
su
Setup time, PCLK active at end of RSTIN (see Note 4 ) t
rst-clk
100 ms
NOTE 4: The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI
clock.