Datasheet

vi
List of Illustrations
Figure Title Page
2–1 PCI2050 GHK Terminal Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 PCI2050 ZHK Terminal Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 PCI2050 PDV Terminal Diagram 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 System Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–2
3–3 PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle 3–3
3–4 Bus Hierarchy and Numbering 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Secondary Clock Block Diagram 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Clock Mask Read Timing After Reset 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Load Circuit and Voltage Waveforms 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 PCLK Timing Waveform 6–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 RSTIN
Timing Waveforms 6–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Shared-Signals Timing Waveforms 6–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .