Datasheet

3–7
3.8.4 Master Abort on Posted Writes
If bit 4 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and a posted write transaction
results in a master abort, then the PCI2050 signals SERR
on the initiating bus. When this occurs, bit 4 of the P_SERR
status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.
3.8.5 Master Delayed Write Time-Out
If bit 5 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and the retry timer expires while
attempting to complete a delayed write, then the PCI2050 signals SERR
on the initiating bus. When this occurs, bit 5
of the P_SERR status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.
3.8.6 Master Delayed Read Time-Out
If bit 6 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while
attempting to complete a delayed read, then the PCI2050 signals SERR
on the initiating bus. When this occurs, bit 6
of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1.
3.8.7 Secondary SERR
The PCI2050 passes SERR from the secondary bus to the primary bus if it is enabled for SERR response, that is,
if bit 8 in the command register (PCI offset 04h, see Section 4.3) is set, and if bit 1 in the bridge control register (PCI
offset 3Eh, see Section 4.32) is set.
3.9 Parity Handling and Parity Error Reporting
When forwarding transactions, the PCI2050 attempts to pass the data parity condition from one interface to the other
unchanged, whenever possible, to allow the master and target devices to handle the error condition.
3.9.1 Address Parity Error
If the parity error response bit (bit 6) in the command register (PCI offset 04h, see Section 4.3) is set, then the PCI2050
signals SERR
on address parity errors and target abort transactions.
3.9.2 Data Parity Error
If the parity error response bit (bit 6) in the command register (PCI offset 04h, see Section 4.3) is set, then the PCI2050
signals PERR
when it receives bad data. When the bridge detects bad parity, bit 15 (detected parity error) in the status
register (PCI offset 06h, see Section 4.4) is set.
If the bridge is configured to respond to parity errors via bit 6 in the command register (PCI offset 04h, see Section 4.3),
then bit 8 (data parity error detected) in the status register (PCI offset 06h, see Section 4.4) is set when the bridge
detects bad parity. The data parity error detected bit is also set when the bridge, as a bus master, asserts PERR
or
detects PERR
.
3.10 Master and Target Abort Handling
If the PCI2050 receives a target abort during a write burst, then it signals target abort back on the initiator bus. If it
receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and disconnects.
Target aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification.
Master aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification.
If a transaction is attempted on the primary bus after a secondary reset is asserted, then the PCI2050 follows bit 5
(master abort mode) in the bridge control register (PCI offset 3Eh, see Section 4.32) for reporting errors.
3.11 Discard Timer
The PCI2050 is free to discard the data or status of a delayed transaction that was completed with a delayed
transaction termination when a bus master has not repeated the request within 2
10
or 2
15
PCI clocks (approximately