Datasheet

2–14
Table 2–10. Miscellaneous Terminals
TERMINAL
NAME
PDV
NO.
GHK/ZHK
NO.
I/O DESCRIPTION
BPCCE 44 P2 I
Bus/power clock control management terminal. When signal BPCCE is tied high and when
the PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary
bus in the B2 power state. The PCI2050 disables the secondary clocks and drives them to
0. When tied low, placing the PCI2050 in the D3 power state has no effect on the secondary
bus clocks.
GPIO3/HSSWITCH
GPIO2
GPIO1
GPIO0
24
25
27
28
K1
K2
K5
K6
I
General-purpose I/O terminals
GPIO3 is HSSWITCH
in cPCI mode.
HSSWITCH
provides the status of the ejector handle switch to the cPCI logic.
HSENUM 127 L14 O Hot-swap ENUM
HSLED 128 K19 O Hot-swap LED output
MS0
155 E17 I Mode select 0
MS1
106 R17 I Mode select 1
NC
102
125
R14
L17
NC These terminals have no function on the PCI2050.
S_M66ENA 153 E18 O
Secondary bus 66-MHz enable terminal. This terminal is always driven low to indicate that
the secondary bus speed is 33 MHz.
Table 2–11. JTAG Interface Terminals
TERMINAL
NAME
PDV
NO.
GHK/ZHK
NO.
I/O DESCRIPTION
TCK 133 J19 I JTAG boundary-scan clock. TCK is the clock controlling the JTAG logic.
TDI 129 K18 I
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG
interface. The new data on TDI is sampled on the rising edge of TCK.
TDO 130 K17 O
JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic
leave the PCI2050.
TMS 132 K14 I JTAG test mode select. TMS causes state transitions in the test access port controller.
TRST 134 J18 I
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a reset
state and initialize the test logic.
Table 2–12. Power Supply Terminals
TERMINAL
DESCRIPTION
NAME PDV NO. GHK/ZHK NO.
DESCRIPTION
GND
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
A6, A12, A14, B5, B10, C9,
C15, D19, F8, F13, F18,
G3, H15, J2, J14, L3, L19,
M6, N18, P6, P13, P14,
P17, T1, U5, U6, U10, V9,
W7, W12, W16
Device ground terminals
V
CC
1, 26, 34, 40, 51, 53, 56, 62,
69, 75, 81, 91, 97, 103, 105,
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
208
A4, A8, A13, A16, B7, C6,
C14, D1, E11, E19, F10,
G17, H18, K3, K15, M1,
M17, N2, N14, P7, P9, P19,
R3, R13, T19, U15, V8, W4,
W6, W11, W13
Power-supply terminal for core logic (3.3 V)
P_V
CCP
124 L18
Primary bus-signaling environment supply. P_V
CCP
is used in
protection circuitry on primary bus I/O signals.
S_V
CCP
135 J17
Secondary bus-signaling environment supply. S_V
CCP
is used in
protection circuitry on secondary bus I/O signals.