Datasheet

6−5
6.5 66-MHz PCI Signal Timing
NOTE: V
test
= 1.5 V for 5-V signals; 0.4 V
CC
for 3.3-V signals
Valid
Valid
V
test
t
v
t
(inval)
t
on
t
off
t
h
t
su
CLK
Output
Input
Figure 6−2. PCI Signal Timing Measurement Conditions
PARAMETER MIN MAX UNIT
t
v(bus)
CLK to signal valid delay—bused signals (see Notes 4, 5, and 6) 2 6 ns
t
v(ptp)
CLK to signal valid delay—point-to-point (see Notes 4, 5, and 6) 2 6 ns
t
on
Float to active delay (see Notes 4, 5, and 6) 2 ns
t
off
Active to float delay (see Notes 4, 5, and 6) 14 ns
t
su(bus)
Input setup time to CLK—bused signal (see Notes 4, 5, and 6) 3 ns
t
su(ptp)
Input setup time to CLK—point-to-point (see Notes 4, 5, and 6) 5 ns
t
h
Input signal hold time from CLK (see Notes 4 and 5) 0 ns
NOTES: 4. See Figure 6−2
5. All primary interface signals are synchronized to P_CLK and all secondary interface signals are synchronized to S_CLK.
6. Bused signals are as follows:
P_AD, P_C/BE
, P_PAR, P_PERR, P_SERR, P_FRAME, P_IRDY, P_TRDY, P_LOCK, P_DEVSEL, P_STOP, P_IDSEL, S_AD,
S_C/BE
, S_PAR, S_PERR, S_SERR, S_FRAME, S_IRDY, S_TRDY, S_LOCK, S_DEVSEL, S_STOP
Point-to-point signals are as follows:
P_REQ
, S_REQx, P_GNT, S_GNTx