Datasheet

6−4
6.4 66-MHz PCI Clock Signal AC Parameters
NOTE: V
t(1)
= 2.0 V for 5-V clocks; 0.5 V
CC
for 3.3-V clocks
V
t(2)
= 1.5 V for 5-V clocks; 0.4 V
CC
for 3.3-V clocks
V
t
(
3
)
= 0.8 V for 5-V clocks; 0.3 V
CC
for 3.3-V clocks
t
(h)
t
c
t
(l)
t
(h)
t
(l)
t
r(SCLK)
t
f(SCLK)
t
c
t
s
t
s
V
t(1)
V
t(2)
V
t(3)
V
t(1)
V
t(2)
V
t(3)
P_CLK
S_CLK
t
r(SCLK)
t
f(SCLK)
Figure 6−1. PCI Clock Signal AC Parameter Measurements
PARAMETER MIN MAX UNIT
t
c
P_CLK, S_CLK cycle time 15 30 ns
t
(h)
P_CLK, S_CLK high time 6 ns
t
(l)
P_CLK, S_CLK low time 6 ns
t
(PSS)
P_CLK, S_CLK slew rate (0.2 V
CC
to 0.6 V
CC
) 1.5 4 V/ns
t
d(SCLK)
Delay from P_CLK to S_CLK 0 7 ns
t
r(SCLK)
P_CLK rising to S_CLK rising 0 7 ns
t
f(SCLK)
P_CLK falling to S_CLK falling 0 7 ns
t
d(skew)
S_CLK0 duty cycle skew from P_CLK duty cycle 0.750 ns
t
sk
S_CLKx to SCLKy 0.500 ns