Datasheet

6−3
6.3 Electrical Characteristics Over Recommended Operating Conditions
PARAMETER TERMINALS OPERATION TEST CONDITIONS MIN MAX UNIT
PCI
3.3 V
I
OH
= −0.5 mA
0.9 V
CC
V
O
High level output voltage
PCI
5 V
I
OH
= −2 mA
2.4
V
V
OH
High-level output voltage
CMOS1
†
I
OH
= −4 mA 2.1
V
CMOS2
‡
I
OH
= −8 mA 2.1
PCI
3.3 V
I
OL
= 1.5 mA
0.1 V
CC
V
Low level output voltage
PCI
5 V
I
OH
= −2 mA
0.55
V
V
OL
Low-level output voltage
CMOS1
†
I
OH
= 4 mA
0.5
V
CMOS2
‡
I
OH
= 8 mA
0.5
I
High level input current
Input terminals V
I
= V
CCP
10
A
I
IH
High-level input current
I/O terminals
§
V V
10
μA
IH
gp
I/O terminals
§
V
I
= V
CCP
10
μ
Input terminals V
I
= GND −1
I
IL
Low-level input current
I/O terminals
§
V
I
= GND −10
μA
I
IL
Low level input current
Pu terminals
¶
V
I
= GND −60
μA
I
OZ
High-impedance output current Output terminals V
O
= V
CCP
or GND ±10 μA
†
CMOS1 includes terminals 24, 25, 27, 28 for PDV- and PDM-packaged devices and K1, K2, K5, K6 for the GHK- and ZHK-packaged devices.
‡
CMOS2 includes terminals 29, 30, 33, 35, 36, 38, 39, 41, 42, 128, 130 for PDV- and PDM-packaged devices and K17, L1, L2, L5, L14, M1, M3,
M6, N1, N2, N6, P1 for the GHK- and ZHK-packaged devices.
§
For I/O terminals, the input leakage current (I
IL
and I
IH
) includes the I
OZ
leakage of the disabled output.
¶
Pu terminals include TDI, TMS, and TRST_L. These are pulled up with internal resistors.