Datasheet

6−1
6 Electrical Characteristics
6.1 Absolute Maximum Ratings Over Operating Temperature Ranges
†
Supply voltage range: V
CC
−0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: P_V
CCP
−0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: S_V
CCP
−0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: CMOS
‡
−0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: PCI
§
−0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
: CMOS
‡
−0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
: PCI
§
−0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual junction temperature, T
J
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
CMOS terminals are 23−25, 27−30, 32, 33, 35, 36, 38, 39, 41, 42, 126−130, 132−134 for PDV- and PPM-packaged devices, and J6, J18, J19,
K1, K2, K5, K6. K14, K17, K18, L1, L2, L5, L14, L15, L17,M1, M3, M6, N1, N2, N6, P1 for the GHK- and ZHK-packaged devices.
§
All signal terminals other than CMOS terminals are PCI terminals.
NOTES: 1. Applies for external input and bidirectional buffers. PCI terminals are measured with respect to V
CCP
instead of V
CC
. The limit is
specified for a dc condition.
2. Applies for external input and bidirectional buffers. PCI terminals are measured with respect to V
CCP
instead of V
CC
. The limit is
specified for a dc condition.