Datasheet

5−13

5.18 Hot-Swap Control Status Register

The hot-swap control status register contains control and status information for cPCI hot swap resources.

Bit 7 6 5 4 3 2 1 0

Name Hot swap control status

Type R R R R R/W R R/W R

Default 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: E6h

Default: 00h

Table 5−13. Hot-Swap Control Status Register Description

BIT TYPE FUNCTION

7 R

ENUM insertion status. When set, the ENUM output is driven by the PCI2050B bridge. This bit defaults to 0, and is set after

a PCI reset occurs, the pre-load of serial ROM is complete, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set

following an insertion when the board implementing the PCI2050B bridge is ready for configuration. This bit cannot be set

under software control.

6 R

ENUM extraction status. When set, the ENUM output is driven by the PCI2050B bridge. This bit defaults to 0, and is set

when the ejector handle is opened and bit 7 is 0. Thus, this bit is set when the board implementing the PCI2050B bridge

is about to be removed. This bit cannot be set under software control.

5−4 R Reserved. Bits 5 and 4 return 0s when read.

3 R/W

LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HS_LED) under normal conditions. However,

for a duration following a PCI_RST

, the HS_LED output is driven high by the PCI2050B bridge and this bit is ignored. When

this bit is interpreted, a 1 causes HS_LED high and a 0 causes HS_LED low.

Following PCI_RST, the HS_LED output is driven high by the PCI2050B bridge until the ejector handle is closed. When

these conditions are met, the HS_LED is under software control via this bit.

2 R Reserved. Bit 2 returns 0 when read.

1 R/W

ENUM interrupt mask. This bit allows the HS_ENUM output to be masked by software. Bits 6 and 7 are set independently

from this bit.

0 = Enable HS_ENUM output

1 = Mask HS_ENUM

output

0 R Reserved. Bit 0 returns 0 when read.