Datasheet

5−12
5.16 HS Capability ID Register
The HS capability ID register identifies the linked list item as the register for cPCI hot-swap capabilities. The register
returns 06h when read, which is the unique ID assigned by the PICMG for PCI location of the capabilities pointer and
the value. In Intel™-compatible mode, this register is read-only and defaults to 00h.
Bit 7 6 5 4 3 2 1 0
Name HS capability ID
Type R R R R R R R R
Default 0 0 0 0 0 1 1 0
Register: HS capability ID
Type: Read-only
Offset: E4h
Default: 06h TI mode
00h Intel-compatible mode
5.17 HS Next-Item Pointer Register
The HS next-item pointer register is used to indicate the next item in the linked list of cPCI hot swap capabilities.
Because this is the last extended capability that the PCI2050B bridge supports, the next-item pointer returns all 0s.
Bit 7 6 5 4 3 2 1 0
Name HS next-item pointer
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: HS next-item pointer
Type: Read-only
Offset: E5h
Default: 00h