Datasheet

5−10
5.13 Power-Management Control/Status Register
The power-management control/status register determines and changes the current power state of the PCI2050B
bridge. The contents of this register are not affected by the internally generated reset caused by the transition from
D3
hot
to D0 state.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power-management control/status
Type R R R R R R R R R R R R R R R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Power-management control/status
Type: Read-only, Read/Write
Offset: E0h
Default: 0000h
Table 5−11. Power-Management Control/Status Register
BIT TYPE FUNCTION
15 R PME status. This bit returns a 0 when read because the PCI2050B bridge does not support PME.
14−13 R
Data scale. This 2-bit read-only field indicates the scaling factor to be used when interpreting the value of the data
register. These bits return only 00b, because the data register is not implemented.
12−9 R
Data select. This 4-bit field is used to select which data is to be reported through the data register and data-scale
field. These bits return only 0000b, because the data register is not implemented.
8 R PME enable. This bit returns a 0 when read because the PCI2050B bridge does not support PME signaling.
7−2 R Reserved. Bits 7−2 return 0s when read.
1−0 R/W
Power state. This 2-bit field is used both to determine the current power state of a function and to set the function
into a new power state. The definition of this is given below:
00 = D0
01 = D1
10 = D2
11 = D3
hot