Datasheet

5−9
5.11 Power-Management Next-Item Pointer Register
The power-management next-item pointer register is used to indicate the next item in the linked list of PCI
power-management capabilities. The next-item pointer returns E4h in CompactPCI mode, indicating that the
PCI2050B bridge supports more than one extended capability, but in all other modes returns 00h, indicating that only
one extended capability is provided.
Bit 7 6 5 4 3 2 1 0
Name Power-management next-item pointer
Type R R R R R R R R
Default 1 1 1 0 0 1 0 0
Register: Power-management next-item pointer
Type: Read-only
Offset: DDh
Default: E4h cPCI mode
00h All other modes
5.12 Power-Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PCI2050B functions
related to power management. The PCI2050B function supports D0, D1, D2, and D3 power states when MS1 is low.
The PCI2050B bridge does not support any power states when MS1 is high.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power-management capabilities
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0
Register: Power-management capabilities
Type: Read-only
Offset: DEh
Default: 0602h or 0001h
Table 5−10. Power-Management Capabilities Register Description
BIT TYPE FUNCTION
15−11 R
PME support. This five-bit field indicates the power states that the device supports asserting PME. A 0 for any of these bits
indicates that the PCI2050B bridge cannot assert PME
from that power state. For the PCI2050B bridge, these five bits return
00000b when read, indicating that PME
is not supported.
10 R
D2 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D2 device power state. This
bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D2 device power state.
9 R
D1 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D1 device power state. This
bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D1 device power state.
8−6 R Reserved. Bits 8−6 return 0s when read.
5 R
Device specific initialization. This bit returns 0 when read, indicating that the bridge function does not require special
initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it.
4 R Auxiliary power source. This bit returns a 0 when read because the PCI2050B bridge does not support PME signaling.
3 R PMECLK. This bit returns a 0 when read because the PME signaling is not supported.
2−0 R
Version. This three-bit register returns the PCI Bus Power Management Interface Specification revision.
001 = Revision 1.0, MS0 = 1
010 = Revision 1.1, MS0 = 0