Datasheet

5−8

5.9 P_SERR Status Register

The P_SERR status register indicates what caused a SERR event on the primary interface.

Bit 7 6 5 4 3 2 1 0

Name P_SERR status

Type R R/W R/W R/W R/W R/W R/W R

Default 0 0 0 0 0 0 0 0

Type: Read-only Read/Write

Offset: 6Ah

Default: 00h

Table 5−9. P_SERR Status Register Description

BIT TYPE FUNCTION

7 R Reserved. Bit 7 returns 0 when read.

6 R/W

Master delayed read time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2

retries on

a delayed read.

5 R/W

Master delayed write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2

retries on

a delayed write.

4 R/W

Master abort on posted write transactions. A 1 indicates that P_SERR was signaled because of a master abort on a posted

write.

3 R/W Target abort on posted writes. A 1 indicates that P_SERR was signaled because of a target abort on a posted write.

2 R/W

Master posted write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 2

retries on

a posted write.

1 R/W Posted write parity error. A 1 indicates that P_SERR was signaled because of parity error on a posted write.

0 R Reserved. Bit 0 returns 0 when read.

5.10 Power-Management Capability ID Register

The power-management capability ID register identifies the linked list item as the register for PCI power management.

The power-management capability ID register returns 01h when read, which is the unique ID assigned by the PCI

SIG for the PCI location of the capabilities pointer and the value.

Bit 7 6 5 4 3 2 1 0

Name Power-management capability ID

Type R R R R R R R R

Default 0 0 0 0 0 0 0 1

Type: Read-only

Offset: DCh

Default: 01h