Datasheet

5−4
5.4 P_SERR Event Disable Register
The P_SERR event disable register is used to enable/disable the SERR event on the primary interface. All events
are enabled by default.
Bit 7 6 5 4 3 2 1 0
Name P_SERR event disable
Type R R/W R/W R/W R/W R/W R/W R
Default 0 0 0 0 0 0 0 0
Register: P_SERR event disable
Type: Read-only, Read/Write
Offset: 64h
Default: 00h
Table 5−4. P_SERR Event Disable Register Description
BIT TYPE FUNCTION
7 R Reserved. Bit 7 returns 0 when read.
6 R/W
Master delayed read time-out.
0 = P_SERR
signaled on a master time-out after 2
24
retries on a delayed read (default).
1 = P_SERR
is not signaled on a master time-out.
5 R/W
Master delayed write time-out.
0 = P_SERR
signaled on a master time-out after 2
24
retries on a delayed write (default).
1 = P_SERR
is not signaled on a master time-out.
4 R/W
Master abort on posted write transactions. When set, bit 4 enables P_SERR reporting on master aborts on posted write
transactions.
0 = Master aborts on posted writes enabled (default)
1 = Master aborts on posted writes disabled
3 R/W
Target abort on posted writes. When set, bit 3 enables P_SERR reporting on target aborts on posted write transactions.
0 = Target aborts on posted writes enabled (default).
1 = Target aborts on posted writes disabled.
2 R/W
Master posted write time-out.
0 = P_SERR
signaled on a master time-out after 2
24
retries on a posted write (default).
1 = P_SERR
is not signaled on a master time-out.
1 R/W
Posted write parity error.
0 = P_SERR
signaled on a posted write parity error (default).
1 = P_SERR
is not signaled on a posted write parity error.
0 R Reserved. Bit 0 returns 0 when read.