Datasheet

5−2

5.2 Extended Diagnostic Register

The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset

both the PCI2050B bridge and the secondary bus.

Bit 7 6 5 4 3 2 1 0

Name Extended diagnostic

Type R R R R R R R W

Default 0 0 0 0 0 0 0 0

Type: Read-only, Write-only

Offset: 41h

Default: 00h

Table 5−2. Extended Diagnostic Register Description

BIT TYPE FUNCTION

7−1 R Reserved. Bits 7−1 return 0s when read.

0 W

Writing a 1 to this bit causes the PCI2050B bridge to set bit 6 of the bridge control register (offset 3Eh, see Section 4.32)

and then internally reset the PCI2050B bridge. Bit 6 of the bridge control register is not reset by the internal reset. Bit 0 is

self-clearing.