Datasheet

5−1

5 Extension Registers

The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration

space (i.e., registers 40h−FFh in PCI configuration space in the PCI2050B bridge). These registers can be accessed

through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the

standard PCI-to-PCI bridge. Mapping of the extension registers is contained in Table 4−1.

5.1 Chip Control Register

The chip control register contains read/write and read-only bits and has a default value of 00h. This register is used

to control the functionality of certain PCI transactions.

Bit 7 6 5 4 3 2 1 0

Name Chip control

Type R R R/W R/W R R R/W R

Default 0 0 0 0 0 0 0 0

Type: Read/Write, Read-only

Offset: 40h

Default: 00h

Table 5−1. Chip Control Register Description

BIT TYPE FUNCTION

7−6 R Reserved. Bits 7−6 return 0s when read.

5 R/W

Transaction forwarding control for I/O and memory cycles.

0 = Transaction forwarding controlled by bits 0 and 1 of the command register (offset 04h, see Section 4.3) (default).

1 = Transaction forwarding is disabled if GPIO3 is driven high.

4 R/W

Memory read prefetch. When set, bit 4 enables the memory read prefetch.

0 = Upstream memory reads are disabled (default).

1 = Upstream memory reads are enabled

3−2 R Reserved. Bits 3 and 2 return 0s when read.

1 R/W

Memory write and memory write and invalidate disconnect control.

0 = Disconnects on queue full or 4-KB boundaries (default)

1 = Disconnects on queue full, 4-KB boundaries and cacheline boundaries.

0 R Reserved. Bit 0 returns 0 when read.