Datasheet
4−15
4.31 Interrupt Pin Register
The bridge default state does not implement any interrupt terminals. Reads from bits 7−0 of this register return 0s.
Bit 7 6 5 4 3 2 1 0
Name Interrupt pin
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Interrupt pin
Type: Read-only
Offset: 3Dh
Default: 00h
4.32 Bridge Control Register
The bridge control register provides many of the same controls for the secondary interface that are provided by the
command register for the primary interface. Some bits affect the operation of both interfaces.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Bridge control
Type R R R R R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Bridge control
Type: Read-only, Read/Write
Offset: 3Eh
Default: 0000h
Table 4−5. Bridge Control Register Description
BIT TYPE FUNCTION
15−12 R Reserved. Bits 15−12 return 0s when read.
11 R/W
Discard timer SERR enable.
0 = SERR
signaling disabled for primary discard time-outs (default)
1 = SERR
signaling enabled for primary discard time-outs
10 R/W
Discard timer status. Once set, this bit must be cleared by writing 1 to this bit.
0 = No discard timer error (default)
1 = Discard timer error. Either primary or secondary discard timer expired and a delayed transaction was discarded from
the queue in the bridge.
9 R/W
Secondary discard timer. Selects the number of PCI clocks that the bridge waits for a master on the secondary interface
to repeat a delayed transaction request.
0 = Secondary discard timer counts 2
15
PCI clock cycles (default)
1 = Secondary discard timer counts 2
10
PCI clock cycles
8 R/W
Primary discard timer. Selects the number of PCI clocks that the bridge waits for a master on the primary interface to repeat
a delayed transaction request.
0 = Primary discard timer counts 2
15
PCI clock cycles (default)
1 = Primary discard timer counts 2
10
PCI clock cycles
7 R
Fast back-to-back capable. The bridge never generates fast back-to-back transactions to different secondary devices. Bit
7 returns 0 when read.
6 R/W
Secondary bus reset. When bit 6 is set, the secondary reset signal (S_RST) is asserted. S_RST is deasserted by resetting
this bit. Bit 6 is encoded as:
0 = Do not force the assertion of S_RST (default).
1 = Force the assertion of S_RST
.