Datasheet

4−14
4.28 Capability Pointer Register
The capability pointer register provides the pointer to the PCI configuration header where the PCI power management
register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The
capability pointer register is read-only and returns DCh when read, indicating the power management registers are
located at PCI header offset DCh.
Bit 7 6 5 4 3 2 1 0
Name Capability pointer register
Type R R R R R R R R
Default 1 1 0 1 1 1 0 0
Register: Capability pointer
Type: Read-only
Offset: 34h
Default: DCh
4.29 Expansion ROM Base Address Register
The PCI2050B bridge does not implement the expansion ROM remapping feature. The expansion ROM base
address register returns all 0s when read.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Expansion ROM base address
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Expansion ROM base address
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Expansion ROM base address
Type: Read-only
Offset: 38h
Default: 0000 0000h
4.30 Interrupt Line Register
The interrupt line register is read/write and is used to communicate interrupt line routing information. Since the bridge
does not implement an interrupt signal terminal, this register defaults to 00h.
Bit 7 6 5 4 3 2 1 0
Name Interrupt line
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Register: Interrupt line
Type: Read/Write
Offset: 3Ch
Default: 00h