Datasheet

4−12

4.23 Prefetchable Memory Limit Register

The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used

to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register

are read/write and correspond to the address bits AD31−AD20. The lower 20 address bits are considered 1s; thus,

the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Prefetchable memory limit

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: 26h

Default: 0000h

4.24 Prefetchable Base Upper 32 Bits Register

The prefetchable base upper 32 bits register plus the prefetchable memory base register defines the base address

of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory

transactions from one interface to the other. The prefetchable base upper 32 bits register must be programmed to

all zeros when 32-bit addressing is being used.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Prefetchable base upper 32 bits

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Prefetchable base upper 32 bits

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write

Offset: 28h

Default: 0000 0000h