Datasheet

4−6
4.8 Primary Latency Timer Register
The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is
a primary PCI bus initiator and asserts P_FRAME
, the latency timer begins counting from 0. If the latency timer expires
before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT
is
deasserted.
Bit 7 6 5 4 3 2 1 0
Name Latency timer
Type R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Register: Latency timer
Type: Read/Write
Offset: 0Dh
Default: 00h
4.9 Header Type Register
The header type register is read-only and returns 01h when read, indicating that the PCI2050B configuration space
adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h−3Fh of configuration space is
considered.
Bit 7 6 5 4 3 2 1 0
Name Header type
Type R R R R R R R R
Default 0 0 0 0 0 0 0 1
Register: Header type
Type: Read-only
Offset: 0Eh
Default: 01h
4.10 BIST Register
The PCI2050B bridge does not support built-in self test (BIST). The BIST register is read-only and returns the value
00h when read.
Bit 7 6 5 4 3 2 1 0
Name BIST
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: BIST
Type: Read-only
Offset: 0Fh
Default: 00h