Datasheet

4−5

4.5 Revision ID Register

The revision ID register indicates the silicon revision of the PCI2050B bridge.

Bit 7 6 5 4 3 2 1 0

Name Revision ID

Type R R R R R R R R

Default 0 0 0 0 0 0 1 0

Type: Read-only

Offset: 08h

Default: 02h (reflects the current revision of the silicon)

4.6 Class Code Register

This register categorizes the PCI2050B bridge as a PCI-to-PCI bridge device (0604h) with a 00h programming

interface.

Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Class code

Base class Sub class Programming interface

Type R R R R R R R R R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Type: Read-only

Offset: 09h

Default: 06 0400h

4.7 Cache Line Size Register

The cache line size register is programmed by host software to indicate the system cache line size needed by the

bridge for memory read line, memory read multiple, and memory write and invalidate transactions. The PCI2050B

bridge supports cache line sizes up to and including 16 doublewords for memory write and invalidate. If the cache

line size is larger than 16 doublewords, the command is converted to a memory write command.

Bit 7 6 5 4 3 2 1 0

Name Cache line size

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

Type: Read/Write

Offset: 0Ch

Default: 00h