Datasheet

4−3
4.3 Command Register
The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is
enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4−2
describes the bit functions in the command register.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Command
Type R R R R R R R/W R/W R R/W R/W R R R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Command
Type: Read-only, Read/Write
Offset: 04h
Default: 0000h
Table 4−2. Command Register Description
BIT TYPE FUNCTION
15−10 R Reserved
9 R/W Fast back-to-back enable. This bit defaults to 0.
8 R/W
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the primary interface.
0 = Disable SERR
driver on primary interface (default)
1 = Enable the SERR
driver on primary interface
7 R
Wait cycle control. Bit 7 controls address/data stepping by the bridge on both interfaces. The bridge does not support
address/data stepping and this bit is hardwired to 0.
6 R/W
Parity error response enable. Bit 6 controls the bridge response to parity errors.
0 = Parity error response disabled (default)
1 = Parity error response enabled
5 R/W
VGA palette snoop enable. When set, the bridge passes I/O writes on the primary PCI bus with addresses 3C6h, 3C8h,
and 3C9h inclusive of ISA aliases (that is, only bits AD9−AD0 are included in the decode).
4 R Memory write and invalidate enable. In a PCI-to-PCI bridge, bit 4 must be read-only and return 0 when read.
3 R
Special cycle enable. A PCI-to-PCI bridge cannot respond as a target to special cycle transactions, so bit 3 is defined as
read-only and must return 0 when read.
2 R/W
Bus master enable. Bit 2 controls the ability of the bridge to initiate a cycle on the primary PCI bus. When bit 2 is 0, the bridge
does not respond to any memory or I/O transactions on the secondary interface since they cannot be forwarded to the
primary PCI bus.
0 = Bus master capability disabled (default)
1 = Bus master capability enabled
1 R/W
Memory space enable. Bit 1 controls the bridge response to memory accesses for both prefetchable and nonprefetchable
memory spaces on the primary PCI bus. Only when bit 1 is set will the bridge forward memory accesses to the secondary
bus from a primary bus initiator.
0 = Memory space disabled (default)
1 = Memory space enabled
0 R/W
I/O space enable. Bit 0 controls the bridge response to I/O accesses on the primary interface. Only when bit 0 is set will
the bridge forward I/O accesses to the secondary bus from a primary bus initiator.
0 = I/O space disabled (default)
1 = I/O space enabled