Datasheet

3−16
3.17 PCI Power Management
The PCI Power Management Specification establishes the infrastructure required to let the operating system control
the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power
of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power
management states, which result in varying levels of power savings.
The four power management states of PCI functions are D0—fully on state, D1 and D2—intermediate states, and
D3—off state. Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from
the device power state of the originating PCI2050B device.
For the operating system to manage the device power states on the PCI bus, the PCI function supports four power
management operations:
• Capabilities reporting
• Power status reporting
• Setting the power state
• System wake-up
The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The
presence of the new capabilities list is indicated by bit 4 in the status register (offset 06h, see Section 4.4) which
provides access to the capabilities list.
3.17.1 Behavior in Low-Power States
The PCI2050B bridge supports D0, D1, D2, and D3
hot
power states when in TI mode. The PCI2050B bridge only
supports D0 and D3 power states when in Intel mode. The PCI2050B bridge is fully functional only in D0 state. In the
lower power states, the bridge does not accept any memory or I/O transactions. These transactions are aborted by
the master. The bridge accepts type 0 configuration cycles in all power states except D3
cold
. The bridge also accepts
type 1 configuration cycles but does not pass these cycles to the secondary bus in any of the lower power states.
Type 1 configuration writes are discarded and reads return all 1s. All error reporting is done in the low power states.
When in D2 and D3
hot
states, the bridge turns off all secondary clocks for further power savings.
When going from D3
hot
to D0, an internal reset is generated. This reset initializes all PCI configuration registers to
their default values. The TI specific registers (40h − FFh) are not reset. Power management registers also are not
reset.