Datasheet

3−15
3.16 GPIO Interface
The PCI2050B bridge implements a four-terminal general-purpose I/O interface. Besides functioning as a
general-purpose I/O interface, the GPIO terminals can read in the secondary clock mask and stop the bridge from
accepting I/O and memory transactions.
3.16.1 Secondary Clock Mask
The PCI2050B bridge uses GPIO0, GPIO2, and MSK_IN to shift in the secondary clock mask from an external shift
register. A secondary clock mask timing diagram is shown in Figure 3−6. Table 3−6 lists the format for clock mask
data.
Bit 15
MSK_IN
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO2
GPIO0
P_RST
S_RST
Figure 3−6. Clock Mask Read Timing After Reset
Table 3−6. Clock Mask Data Format
BIT CLOCK
[0:1] S_CLKOUT0
[2:3] S_CLKOUT1
[4:5] S_CLKOUT2
[6:7] S_CLKOUT3
8 S_CLKOUT4
9 S_CLKOUT5
10 S_CLKOUT6
11 S_CLKOUT7
12 S_CLKOUT8
13 S_CLKOUT9 (PCI2050B S_CLK input)
[14:15] Reserved
3.16.2 Transaction Forwarding Control
The PCI2050B bridge will stop forwarding I/O and memory transactions if bit 5 of the chip control register (offset 40h,
see Section 5.1) is set to 1 and GPIO3 is driven high. The bridge completes all queued posted writes and delayed
requests, but delayed completions are not returned until GPIO3 is driven low and transaction forwarding is resumed.
The bridge continues to accept configuration cycles in this mode. This feature is not available when in CompactPCI
hot-swap mode because GPIO3 is used as the HS_SWITCH
input in this mode.